1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a power-on detecting circuit.
2. Description of Related Art
Many types of electrically rewritable and non-volatile memories (EEPROM) are known. A NAND-type flash memory is one of such EEPROMs. Usually, a flash memory has a power-on reset circuit therein for automatically initializing the internal circuit in response to power-on. There has already been provided a memory technique that initial setup data storage area is set in a memory cell array. There has also been provided a flash memory in which system start-up data (i.e., system boot data) storage area is set in a memory cell array, and the boot data is automatically read out by detecting power-on. For example, refer to Japanese Patent Application Laid Open (kokai) 2003-162453).
Power-on detecting circuits employed in the conventional flash memories are usually configured to detect that a voltage generated by resistance-dividing the external power supply voltage has become higher than a predetermined level, thereby outputting a power-on signal. In response to this power-on signal, an internal power circuit is activated, and above-described initial setup operations and boot data reading are performed.
It is required of the power-on detecting circuit equipped in the flash memory to be responsible to various external power supply voltages with different rising properties and different voltage levels. Unfortunately, every conventional power-on detecting circuit utilized in general outputs a power-on signal output timing of which is varied in correspondence with rising characteristics and voltage levels of the external power supply voltages. For example, in case the external power supply voltage has an abrupt rising property, a power-on signal will be output at an early timing after power-on. This fact causes the internal power supply circuit, which is activated by the power-on signal, to be impossible to output a stable internal power supply voltage. If the internal power supply voltage is not stabilized, the power-on reset operation will be harmfully influenced. In detail, starting a boot data read operation before the internal power supply voltage has been stabilized, the operation becomes erroneous.